This paper proposes a theoretical study and a full
overview of the design, evaluation and optimization of a PUF
based on transient element ring oscillators (TERO-PUF). We
show how, by following some simple design rules and strategies,
designers can build and optimize a TERO-PUF with state of the
art PUF characteristics in a standard CMOS technology. To this
end, we analyzed the uniqueness, steadiness and randomness of
responses generated from 30 test chips in a CMOS 350nm process
in nominal and corner voltage and temperature conditions.
Response generation schemes are proposed to optimize PUF
performances and reduce its area without noticeable loss in its
output quality. In particular, we show that the large area of the
basic blocks in the TERO-PUF is balanced by the high level
of entropy extracted in each basic block. Thus, the length of
the response to the same challenge is increased. Guidelines are
provided to balance reliability and randomness of the responses
and the design area.
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